(1) Field of the Invention
This invention relates to a method of manufacturing an MIS (Metal-Insulator-Semiconductor) type semiconductor device and more specifically to a method of forming an impurity region for an MIS type device in a semiconductor substrate using an ion implantation method.
(2) Description of the Prior Art
With progress in miniaturization of elements for realizing high integration density of a semiconductor device, ion implantation has been used extensively as a means for accurately forming an impurity region having a desired impurity concentration profile.
The ion implantation method has diversified merits as compared with the thermal diffusion method. For example, fluctuation of sheet resistance of the implantation layer can be reduced, impurity concentration can be increased, processing can be executed at a comparatively low temperature and within a short period of time, junction depth can be controlled with excellent accuracy, a complicated impurity profile can be formed rather easily, and pattern accuracy can be improved.
It has been found that the solid solubility at which an impurity becomes active electrically in a semiconductor material lies at a point lower than the metallurgical solid solubility at which the impurity is capable of being dissolved into the semiconductor material under the thermal equilibrium state, when the impurity is implanted into a semiconductor base material. This solid solubility is called an electrically active solubility, and it is about, for example, 2.about.6.times.10.sup.20 atm/cm.sup.3 when arsenic (As) is implanted as an impurity into silicon (Si). When impurity atoms exceeding the electrically active solubility exist in the impurity region, such excessive impurity atoms become carrier traps or lower the mobility of carriers, thereby increasing the sheet resistance of the impurity introduced region or the leakage current, and accordingly degrading peformance of the completed semiconductor elements. An MIS type semiconductor device, particularly an MIS IC, is designed in many cases so that the impurity region functions as wiring. Therefore, it is often desirable to keep the sheet resistance of the impurity region as low as possible even if this requires increasing integration density.
Conventionally, when forming the n-channel type MIS-IC, etc., by the ion implantation method with As used as the impurity, as shown in FIG. 1(a), a gate oxide film 4 is formed at a thickness of about 500 .ANG. on a surface portion of a p-type Si substrate 3 having an impurity concentration of about 10.sup.15 atm/cm.sup.3. The gate oxide film 4 is exposed and surrounded by a field isolation oxide film 1 and a p.sup.+ -type channel stopper region 2. A polycrystalline Si gate electrode 5 is formed on the gate oxide film 4 to a thickness of about 3000.about.4000 .ANG.; thereafter arsenic ions (As.sup.+ are implanted with a dosage of about 4.times.10.sup.15 atm/cm.sup.2 at an energy in the range of 100.about.150 KeV, for example 120 KeV, to the surface of the p-type Si substrate 3 through the gate oxide film 4 with the gate electrode 5 used as the mask (where 6' is the As.sup.+ implanting region).
FIG. 2 is a graph of an As concentration profile of the As implanting region thus formed. In this figure, the curve shows the concentration of As vs. depth, S is metallurgical solid solubility at 1100.degree. C., EAS is electrically active solubility, SiO.sub.2 denotes a gate oxide film region, and Si denotes a p-type Si substrate region.
In the existing method, As is implanted in such amount as is required to obtain the desired low sheet resistance, without particular consideration of the resulting electrically active solubility. Therefore, as shown in FIG. 2, the concentration of As at the peak value is larger than the electrically active solubility. However, in the existing method, As is redistributed by a thermal treatment in succeeding process steps and, as a result, the peak value of the concentration of As is lowered.
The substrate is then heated by an electric furnace for about 30 min at a temperature as high as about 1000.degree. C. in a nitrogen (N.sub.2) ambient and is annealed to activate the As.sup.+ implanted region 5. As explained above, As is redistributed in this process. FIG. 1(b) ia a cross-sectional view illustrating the condition after such annealing. In this figure, 6 is the As diffused region (n+-type source/drain region) formed by annealing the As implanting region. As shown in the figure, the implanted As is diffused by the annealing process, so that the As diffused region (source/drain region) 6 is formed to a depth (d) of about 4000 .ANG.. This As diffused region expands laterally by the dimension l (which is almost tantamount to the depth) from the mask end 7 (l is about 3000 .ANG.). For this reason, the existing method has a problem in that the lateral diffusion interferes with high integration density of elements.
Moreover, the high temperature-heated annealing method has been accompanied by the problem that the lateral diffusion changes in dimension because the concentration profile of As in the diffused region cannot be controlled strictly, and element characteristics fluctuate due to the change in the length of the channel of the MIS type transistor.
An example of a method which has been attempted in order to alleviate the above problems is the shallow formation of a diffused region. In this case, however, the total amount of As in the diffused region runs short and accordingly the desired low sheet resistance value cannot be obtained. Another example of a method which has been conducted is where the ion-implanted impurity is irradiated with an energy beam and is activated without any substantial redistribution of impurity. When redistribution of the impurity does not occur, the impurity does not expand laterally during the annealing process. However, an impurity implanted in such a concentration as to exceed the electrically active solubility is not activated because it is never reduced to a concentration lower than the electrically active solubility by redistribution. Nevertheless, if the ion implantation method is used, such a large amount of impurity must be implanted that the peak concentration exceeds the electrically active solubility, in order to obtain the low sheet resistance which is usually desired in an MIS type semiconductor device.